1. Field of Invention
The present invention relates to a package and method of manufacturing the same. More particularly, the present invention relates to a chip package and method of manufacturing the same.
2. Description of Related Art
The reduction in dimension and increase in density of semiconductor components requires even higher packaging skills. The demand of smaller electronic device has increased, and the packaging technique evolves along the course. Three-dimensional semiconductor chip package becomes an effective solution to meet the ever-shrinking dimension.
In a three-dimensional semiconductor chip package, the semiconductor chip is stacked vertically, and the electrical connection is achieved by through package via (TPV). In this way, the length of conductive wires between chips and component size will shrink. Three-dimensional semiconductor chip package technique integrates semiconductor chips with different functions to improve produce efficiency, reduce the package size and reach higher component density. In other words, three-dimensional semiconductor chip package technique can be utilized in even smaller device having higher density, multiple functions, and higher efficiency. In general, three-dimensional semiconductor chip package includes semiconductor chip, interposer having TPV and other substrates. The semiconductor chip is attached to one side of the interposer by soldering to a bump. The bump provides the electrical connection between the integrated circuit chip and the interposer. The other side of the interposer can be electrically connected to a printed circuit board or other integrated circuit chips through soldering balls. By the TPVs, the semiconductor chip and printed circuit board or any other integrated circuit chips on either side of the interposer and can be integrated.
In the integration of the semiconductor chip and the interposer, the soldering bump is typically a specific alloy. The metal phase conversion is achieved by eutectic bonding. Eutectic bonding is a specific diffusion bonding. The alloy can diffuse and mix under a temperature that is lower than any of the solute. Under about 400 to 500 degree Celsius which is relatively low, the metal interface bonding between the integrated circuit chip and the interposer can be established. However, eutectic bonding process has strict requirement on temperature, heating cycles or other parameters in the annealing process such that if the soldering bump is slightly deformed in the process, a mechanical force is generated and greatly affects the interface bonding. Therefore the soldering bump between the semiconductor chip and the interposer is prone to fail in the joining or break apart. There is an urgent call to replace the soldering bump of the semiconductor chip package with new material and process. New materials also brings about issues that is await to be solved.